This invention relates generally to integrated circuits, and more particularly to balancing differential signal lines in integrated circuits.
Integrated circuit static random access memories (SRAMs) are used in a variety of applications today. In particular, high speed synchronous SRAMs are used in such applications as caches for computer systems, workstations, and the like. These cache memories provide a high-speed storage of data or instructions that are likely to be reused. As integrated circuit technology,has improved, microprocessors have correspondingly increased in speed. As microprocessor speed increases, the access time of the SRAMs must decrease to provide efficient cache storage.
The supply voltage of SRAMs to is being lowered to reduce energy consumption and the generation of heat. For example, some SRAMs operate with a supply voltage of about 1.8 volts. As a result, the voltage differential on the bit line pairs is becoming increasingly low. The importance of signal separation on the bit lines to maintain margins and reliability is thus heightened.
SRAMs and other memory products typically have long differential pairs of signal lines or bit lines configured over an array of memory cells. A problem arises wherein these differential pairs experience crosstalk due to the sidewall coupling with adjacent differential pairs and with the underlying substrate. This crosstalk results in decreased performance, degradation in signal separation, and reduction in speed.
One approach to reduce the signal degradation due to crosstalk has been to twist the differential pairs at intervals to expose each routing of the pair to the same capacitive coupling. A problem with the traditional approach of twisting metal routings, however, is that in each twist, one signal transitions between multiple layers of metal while the other does not. Each layer of metal may have different resistivities. In addition, each twist requires the signal on one routing to pass through a via, which may have a different resistivity as well. These transitions cause resistive and capacitive imbalances in the differential pair, which may also result in signal degradation and reduced signal separation.
In order to compensate for the undesirable effects of the traditional twist design, one could add additional twists. This solution is not suitable to many applications such as memory devices, however, since many bit cells will be followed by an odd number of twists, resulting in asymmetry and many of the same problems associated with a single traditional twist.